Title
A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface
Abstract
In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.
Year
DOI
Venue
2008
10.1109/ESSCIRC.2008.4681812
Proceedings of the European Solid-State Circuits Conference
Keywords
DocType
ISSN
bit error rate,chip,fir filters,code division multiple access,digital filter,fir filter,broadband networks,spread spectrum communication,satisfiability,gsm,time constant,digital filters,cmos integrated circuits,transceivers,direct conversion receiver
Conference
1930-8833
Citations 
PageRank 
References 
3
0.59
3
Authors
29