Name
Abstract | ||
|---|---|---|
This paper presents a clocked, regenerative comparator in a 1.5V/0.12 mu m CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10(-9). The power consumption of the comparator is 422 mu W at 2GHz and 584 mu W at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ESSCIRC.2007.4430329 | Proceedings of the European Solid-State Circuits Conference |
Keywords | DocType | ISSN |
amplifiers,cmos integrated circuits,standard deviation,bit error rate | Conference | 1930-8833 |
Citations | PageRank | References |
1 | 0.50 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bernhard Goll | 1 | 15 | 6.08 |
| Horst Zimmermann | 2 | 29 | 15.60 |