Paper Info
Title
Low power CMOS power amplifier design for RFID and the Internet of Things.
Abstract
Designing power amplifiers with low power consumption, high efficiency and integration is an important topic with significant impact on communication and circuit research areas. In order to make transceivers more powerful with lower cost and higher integration, a CMOS power amplifier working from 3.5GHz to 4.5GHz is proposed. Cascode driver stage is adopted to give the power amplifier high output gain ability. The output stage is designed as Class A, which makes the proposed power amplifier in a significantly high linearity level. Furthermore, this paper gives a comparative study of the performance of different power amplifier classes. Simulation results show that the proposed power amplifier has 31.2% more power added efficiency (PAE) and 12.6dB output power gain, respectively. The proposed power amplifier has high linearity and efficiency, which are suitable for Radio Frequency Identification (RFID) and Internet of Things (IoT) applications.
Year
DOI
Venue
2016
10.1016/j.compeleceng.2015.06.006
Computers & Electrical Engineering
Keywords
Field
DocType
CMOS,Power amplifier,Transceiver,Wireless communication
Power gain,Computer science,Direct-coupled amplifier,Electronic engineering,Linear amplifier,Power supply rejection ratio,Power-added efficiency,RF power amplifier,Electrical engineering,Power bandwidth,Amplifier
Journal
Volume
Issue
ISSN
52
C
0045-7906
Citations 
PageRank 
References 
0
0.34
2
Authors
4
Name
Order
Citations
PageRank
Chenyuan Zhao1274.57
J. Liu26415.00
fangyang shen372.51
Yang Yi415926.70