Paper Info
Title
Hierarchical approach for hybrid wireless Network-on-chip in many-core era
Abstract
Due to high latency and high power consumption in long hops between operational cores of Network-on-Chips (NoCs), the performance of such architectures has been limited. Billions of transistors available on a single chip present opportunities for new levels of computing capability. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless NoC has been emerged. Employing wireless communication links between cores, wireless NoC has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in wireless NoCs. Thus, in this paper, we introduce a hybrid wireless NoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are handled almost by single-hop wireless links. Simulation results show that HiWA efficiently reduces power consumption by 39% in comparison with a traditional wireless NoC, called WiNoC, while still achieves 16% lower packet latency than conventional NoC.
Year
DOI
Venue
2016
10.1016/j.compeleceng.2015.10.007
Computers & Electrical Engineering
Keywords
Field
DocType
System-on-Chip,Network-on-Chip,Wireless Network-on-Chip,Architecture,Ant Colony Optimization,Max–Min Ant System
Key distribution in wireless sensor networks,Wireless network,Wireless,Computer science,Network packet,Network on a chip,Computer network,Communications system,Real-time computing,Wireless WAN,Wi-Fi array,Embedded system
Journal
Volume
Issue
ISSN
51
C
0045-7906
Citations 
PageRank 
References 
13
0.56
25
Authors
4
Name
Order
Citations
PageRank
Amin Rezaei1688.33
Masoud Daneshtalab260960.88
Farshad Safaei39519.37
Danella Zhao4322.00