Name
Title | ||
|---|---|---|
A 12b 238kS/s SAR ADC with novel built-in digital calibration method for EEG acquisition applications |
Abstract | ||
|---|---|---|
A new built-in digital calibration method is proposed in this paper for a split capacitive DAC in SAR ADCs. By using the LSB-side of split CDAC to measure the capacitor mismatch in MSB-side, it saves any auxiliary CDAC for mismatch calibration and also reduces the chip area. In this design, the digital part is implemented by Verilog HDL and synthesized a Global Foundry 0.13 μ m CMOS technology. The simulation results show that with the supply voltage of 0.9V, the ADC consumes 25.4 μW at the sampling rate of 238kS/s. And the SNDR is 68dB with 15.12kHz input sinusoid signal using the proposed calibration method, showing the corresponding figure-of-merit of 52fJ/conv·step. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/BioCAS.2015.7348308 | 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS) |
Keywords | Field | DocType |
EEG,SAR ADC,split DAC,calibration,capacitor mismatch | Flight dynamics (spacecraft),Computer science,Sampling (signal processing),Capacitive sensing,Chip,Electronic engineering,CMOS,Successive approximation ADC,Verilog,Calibration | Conference |
ISSN | Citations | PageRank |
2163-4025 | 0 | 0.34 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaolin Yang | 1 | 1 | 2.78 |
| Zhou Xiao | 2 | 84 | 19.21 |
| Menglian Zhao | 3 | 16 | 6.31 |
| Xiaobo Wu | 4 | 5 | 6.74 |