Name
Abstract | ||
|---|---|---|
This work aims to study different analytical and numerical models to estimate effective W/L ratio considering transistors with enclosed gate geometry, suitable for implementation into standard Process Design Kits (PDK). Different geometries emphasizing the output (I
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) and the transfer (I
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) characteristics were studied. Besides estimating the aspect ratio, the source and the drain areas are also included in the equivalent transistor. The results show that, if considering DC simulations only, this modification does not significantly change the output behavior. The simulation technique was implemented using commercial available PDK's and design and verification CAD tools targeted only toward the two-edged transistors, allowing automated ELT simulation. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/LASCAS.2015.7250407 | 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | Field | DocType |
ELT,gate-enclosed layout,aspect ratio calculation,square MOSFET | Cad tools,Numerical models,Computer science,Electronic engineering,Process design,Transistor | Conference |
ISSN | Citations | PageRank |
2330-9954 | 2 | 0.60 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pablo Vaz | 1 | 3 | 1.35 |
| alberto wiltgen junior | 2 | 2 | 0.60 |
| Gilson I. Wirth | 3 | 83 | 17.98 |