Name
Title | ||
|---|---|---|
New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A |
Abstract | ||
|---|---|---|
Proposed innovation gives a faster, lower depth, lower power and lower area solution for addition. The paper describes two novel static gates developed for 4-bit Majority Carry Generate (MCG) and Majority Carry Propagate (MCP) operation in a single gate depth. Derivation of a novel 72-bit CL2A within 6 gate-depth, using MCG, MCP and a novel sparse5 (5x2(n)) algorithm with a variable sparse is described. Implementation of a novel 64-bit CL3A within 5 gate-depth, by extending CL2A with progressive sparse 1+3(0) + 3(1) + 3(2) +...3(n) algorithm is described. Silicon evaluation of an 8-bit application for the CL2A is presented in 32nm. Post-layout results of 64-bit CL2A and 64-bit CL3A against Ling-Carry-select adder are presented in 14nm along with the advantages and limitations. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/MWSCAS.2013.6674915 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
adders | Adder,Computer science,Parallel computing,Serial binary adder,Carry-save adder | Conference |
ISSN | Citations | PageRank |
1548-3746 | 1 | 0.37 |
References | Authors | |
1 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| l m k garimella | 1 | 1 | 0.37 |
| Sri Raga Sudha Garimella | 2 | 5 | 2.31 |
| k duda | 3 | 1 | 0.37 |
| Eric S. Fetzer | 4 | 35 | 1.98 |