Name
Abstract | ||
|---|---|---|
In this study we present 3T and 3T1D DRAM cells designed using FinFET technology. Overall, the 3T DRAM cell has a 43.6% faster write speed than the 3T1D cell and uses less dynamic current (30.4% less write current and 14.6% less read current). The FinFET 3T1D DRAM cell offers a 16.7% faster read speed and 48.6% less read leakage current than the 3T1D cell. The 3T DRAM cell offers less variation in delays, up to 37% less than the 3T1D cell for write delay, due to parameter corner simulations. Overall for a system, the 3T FinFET DRAM cell is more promising due to its low dynamic current and significantly shorter write speed which leads to a smaller maximum delay. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MWSCAS.2012.6292055 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
capacitance,logic gates,cmos integrated circuits | Dynamic random-access memory,Dram,Logic gate,Capacitance,Leakage (electronics),Computer science,CMOS,Electronic engineering,MOSFET,CAS latency | Conference |
ISSN | Citations | PageRank |
1548-3746 | 2 | 0.36 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| colby m gerik | 1 | 2 | 0.36 |
| Michael A. Turi | 2 | 11 | 3.77 |
| Jose G. Delgado-Frias | 3 | 23 | 8.75 |