Name
Abstract | ||
|---|---|---|
NAND flash memory has very distinct characteristics (such as the out-of-place update and the endurance problem) that can damage the performance and lifetime of NAND flash memory. In order to improve the performance and lifetime of NAND flash memory, a flash-aware write buffer is used to buffer the frequently accessed data and reduce a lot of write and erase operations. Based on our observations, the page read cache mode and the multi-channel I/O parallelism can improve the current flash-aware write buffer schemes. In the paper, we consider the file-aware information and integrate the concept of the page read cache mode and the multi-channel I/O parallelism into the design of the write buffer schemes. According to the experimental results, the proposed method can improve the effectiveness of the current flash-aware write buffer schemes. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2811411.2811473 | Proceedings of the 2015 Conference on research in adaptive and convergent systems |
Keywords | Field | DocType |
write buffer | Nand flash memory,Flash file system,Cache,Computer science,Real-time computing,Write buffer,Write combining,Racetrack memory | Conference |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chin-Hsien Wu | 1 | 419 | 47.93 |
| Kuo-Yi Chao | 2 | 0 | 0.34 |