Name
Title | ||
|---|---|---|
Design and validation of a 10-bit current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS |
Abstract | ||
|---|---|---|
A 10-bit 50 MS/s current-mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Due to the absence of a switched capacitor feedback DAC, the value of the sampling capacitance can be chosen solely based on the kT/C noise required to achieve a certain performance. Then by designing the input Gm stage for a wide differential input voltage range, the resulting sampling capacitance value can be made significantly smaller compared to a conventional switched capacitor SAR ADC. Moreover, the presented design requires neither an external reference voltage to bias the Gm stage output nor a low-impedance DAC-reference voltage. To validate the proposed approach, a prototype 10-bit ADC is fabricated in a 90 nm TSMC CMOS process. Measured results of the ADC show an SFDR of 58.4 dB at 50 MS/s, while consuming 6 mW from a 1.2 /1.8 V supply. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/s10470-016-0788-z | Analog Integrated Circuits and Signal Processing |
Keywords | Field | DocType |
capacitors,switches,cmos integrated circuits,cmos technology | Capacitor,Capacitance,Computer science,Voltage reference,Voltage,CMOS,Switched capacitor,Spurious-free dynamic range,Successive approximation ADC,Electrical engineering | Conference |
Volume | Issue | ISSN |
89 | 2 | 0925-1030 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| abdelrahman elkafrawy | 1 | 0 | 0.34 |
| Jens Anders | 2 | 60 | 24.75 |
| Maurits Ortmanns | 3 | 501 | 114.46 |