Name
Abstract | ||
|---|---|---|
A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic design methodology to maximize the locking range over power consumption ratio is proposed. The test chip core area is only 25.6×24.8μm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
and measurements repeated over several samples demonstrate an operating frequency range from 25GHz to 102GHz with a maximum power consumption of 5.64mW from a 0.9V supply. The frequency band from 44.3GHz to 90GHz is covered in only three steps with a minimum fractional bandwidth in exceed of 20% and power consumption less than 4.7mW demonstrating the effectiveness of the proposed design techniques. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASSCC.2015.7387511 | 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | Field | DocType |
frequency divider,mm-Wave,CML dynamic latch,inductorless,low power,wideband,E-band,CMOS | Wideband,Operating frequency,Frequency band,Computer science,Real-time computing,Electronic engineering,Chip,CMOS,Bandwidth (signal processing),Transistor,Maximum power principle,Electrical engineering | Conference |
Citations | PageRank | References |
2 | 0.44 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marco Vigilante | 1 | 23 | 3.19 |
| Patrick Reynaert | 2 | 463 | 76.50 |