Name
Abstract | ||
|---|---|---|
Reducing test costs of analog and RF circuits is a complex challenge, for which intuitive solution is to reduce test time. However, such reduction usually leads to a degradation of measurement accuracy not easy to handle when no model is available to understand the impact of the reduction.This work presents a novel method to evaluate the impact of test time reduction on yield accuracy, using only measured values and easy-to-obtain uncertainty models. The results proposed by this method provide a balance between test time reduction and yield accuracy.The proposed method is applied on the evaluation of a SNR measurement and provides a representation of the impact of measurement time reduction on yield loss. |
Year | Venue | Keywords |
|---|---|---|
2015 | 2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | Analog test, Test cost reduction, Yield analysis |
Field | DocType | ISSN |
Analogue circuits,Noise measurement,Computer science,Signal-to-noise ratio,Electronic engineering,Balancing test,Accuracy and precision,Electronic circuit,Probability density function,Reliability engineering,Cost reduction | Conference | 2472-467X |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| matthieu verdy | 1 | 0 | 0.34 |
| Dominique Morche | 2 | 84 | 18.00 |
| Emeric de Foucauld | 3 | 18 | 6.85 |
| S. Lesecq | 4 | 3 | 1.79 |
| jeanpascal mallet | 5 | 0 | 0.34 |
| cedric mayor | 6 | 0 | 0.34 |