Name
Title | ||
|---|---|---|
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter |
Abstract | ||
|---|---|---|
This paper presents a low-power BW-tracking semi-digital PLL. The design features independently adjustable proportional and integral controller paths. The digital information provided by the storage cells in the I-path are used to let the PLL bandwidth and phase margin track the VCO frequency. The proposed switching scheme in the P-path provides a quiet output in the locked state significantly reducing update jitter. In contrast to classical analog charge pump PLLs, the proposed concept features low design complexity and small area requirements and does not require external components. In contrast to digital PLLs, the proposed architecture allows for an excellent phase noise performance without the need for highly scaled CMOS technologies. As a proof-of-concept of the proposed architecture, a PLL prototype realized in a low cost 0.4 μm CMOS technology is presented, which achieves a measured integrated rms jitter of only 700 fs competing with the state-of-the-art in deep submicron CMOS technologies. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/NORCHIP.2015.7364357 | 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) |
Keywords | Field | DocType |
BW-tracking semidigital PLL,near-optimal VCO phase noise shaping,low-cost CMOS,phase jitter,size 0.4 mum,time 700 fs | Phase-locked loop,Computer science,PLL multibit,Phase noise,Electronic engineering,Voltage-controlled oscillator,Real-time computing,CMOS,Phase margin,Jitter,Phase frequency detector | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Suhaib A. Fahmy | 1 | 582 | 57.16 |
| markus dietl | 2 | 1 | 0.77 |
| Puneet Sareen | 3 | 7 | 2.50 |
| Maurits Ortmanns | 4 | 501 | 114.46 |
| Jens Anders | 5 | 60 | 24.75 |