Paper Info
Title
On the design of optimal 2D filters for efficient hardware implementations of image processing algorithms by using power-of-two terms
Abstract
In this paper, we present a general approximation for 2D filters by using only power-of-two terms. This enables to easily implement these filters in electronic devices such as FPGA and ASIC just by using simple hardware shifters and adders/subtractors. Consequently, no division and no multiplication operators are required, which can reduce the memory and the power needed for computing operations such as convolution. Instead of using only additions and power-of-two terms for representing a number like in the standard binary decomposition, our model also uses subtractions for representing and approximating numbers. In addition, we propose a binary tree structure for computing a minimal representation in power-of-two terms in such a way that hardware shifters used for performing a convolution with a low-pass filter for example are well reduced to their minimum. Based on some experiments performed for contrast enhancement, which is a common image processing operation, we have noticed that good results can be obtained using our approximation in terms of image quality, hardware resources, and power consumption when compared to some other binary representations.
Year
DOI
Venue
2019
10.1007/s11554-015-0550-2
Journal of Real-time Image Processing
Keywords
Field
DocType
Number representation, Multipliers, Logical shift operators, FPGA, 2D filters, Image processing, Contrast enhancement, Minimal representation, Binary tree
Computer science,Convolution,Image processing,2D Filters,Algorithm,Binary tree,Real-time computing,Multiplication,Digital image processing,Computer engineering,Power of two,Binary number
Journal
Volume
Issue
ISSN
16
2
1861-8219
Citations 
PageRank 
References 
1
0.40
15
Authors
2
Name
Order
Citations
PageRank
alain hore110.40
Orly Yadid-Pecht223035.79