Name
Abstract | ||
|---|---|---|
The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and. the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and. on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/JSSC.2002.801186 | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Keywords | DocType | Volume |
clock and data recovery, CDR, fiber-optic communication receiver, InPHBT, limiting amplifier, phase detector, VCO | Journal | 37 |
Issue | ISSN | Citations |
9 | 0018-9200 | 3 |
PageRank | References | Authors |
0.60 | 0 | 12 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| George Georgiou | 1 | 3 | 0.93 |
| Y. Baeyens | 2 | 23 | 7.08 |
| Young-Kai Chen | 3 | 70 | 16.40 |
| A. H. Gnauck | 4 | 22 | 6.29 |
| c gropper | 5 | 3 | 0.60 |
| P. Paschke | 6 | 8 | 1.57 |
| r pullela | 7 | 15 | 3.29 |
| m reinhold | 8 | 3 | 0.60 |
| C. Dorschky | 9 | 16 | 9.08 |
| j p mattia | 10 | 3 | 0.60 |
| t w von mohrenfels | 11 | 3 | 0.60 |
| c schulien | 12 | 3 | 0.60 |