Name
Title | ||
|---|---|---|
A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration |
Abstract | ||
|---|---|---|
This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing a... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.873862 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Pipelines,Calibration,Clocks,Analog-digital conversion,Sampling methods,Low voltage,Signal sampling,Prototypes,CMOS process,Signal processing | Journal | 41 |
Issue | ISSN | Citations |
7 | 0018-9200 | 19 |
PageRank | References | Authors |
2.86 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kwi-Dong Kim | 1 | 70 | 10.44 |
| Jong-Kee Kwon | 2 | 158 | 23.10 |
| Jongdae Kim | 3 | 102 | 17.00 |
| Seunghoon Lee | 4 | 244 | 61.57 |