Name
Abstract | ||
|---|---|---|
Linear (order-1) function evaluation schemes, such as bipartite and multipartite tables, are usually effective for low-precision approximations. For high-output precision, the lookup table size is often too large for practical use. This brief investigates the so-called (M, p, k) scheme that reduces the range of an input argument to a very small interval so that trigonometric functions can be approximated with very small lookup tables and a few additions/subtractions. An optimized hardware architecture is presented and implemented in both a field-programmable gate array device and standard-cell-based technology. Experimental results show that the proposed scheme achieves more than a 50% reduction in total chip area compared with the best linear approach for a 24-bit evaluation. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCSII.2014.2331094 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Keywords | Field | DocType |
Bipartite table, field-programmable gate array (FPGA), trigonometric function evaluation | Lookup table,Trigonometric functions,Multipartite,Bipartite graph,Algorithm,Chip,Gate array,Mathematics,Hardware architecture | Journal |
Volume | Issue | ISSN |
61 | 9 | 1549-7747 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Milos D. Ercegovac | 1 | 387 | 56.83 |
| Nicolas Brisebarre | 2 | 106 | 13.20 |
| Jean-Michel Muller | 3 | 466 | 66.61 |
| Dong Wang | 4 | 181 | 15.20 |