Name
Abstract | ||
|---|---|---|
This paper is devoted to VLSI implementation of a staged decoder for Block-Coded Modulation (BCM). We first review a general parallel and pipelined implementation of the decoder and we identify the parameters to be considered for optimization. A particular BCM scheme, based on the 8-PSK signal set, is chosen for a case study. Several ideas are described leading to a code-optimized design, and hardware implementation is shown. Next, we evaluate the performance of our design. In particular it is shown that, by exploiting regularity, a simple structure which achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2 standard cells CMOS technology. Further optimization and simple stacking of ten processors on a single chip in a block-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates). |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1007/BF02107053 | VLSI Signal Processing |
Keywords | Field | DocType |
Processing Element,Systolic Array,Viterbi Algorithm,Throughput Rate,VLSI Signal Processing | Throughput (business),Computer science,Parallel computing,Systolic array,Modulation,Chip,CMOS,Real-time computing,Transistor,Very-large-scale integration,Viterbi algorithm | Journal |
Volume | Issue | ISSN |
11 | 3 | 0922-5773 |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Giuseppe Caire | 1 | 9797 | 807.61 |
| Ventura-Traveset, J. | 2 | 78 | 19.82 |
| J. Murphy | 3 | 0 | 0.68 |
| S. Y. Kung | 4 | 18 | 3.85 |