Name
Abstract | ||
|---|---|---|
In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data. |
Year | Venue | Keywords |
|---|---|---|
2002 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | floorplanning, timing-driven layout, buffer insertion, wire sizing, simulated annealing |
DocType | Volume | Issue |
Journal | E85A | 12 |
ISSN | Citations | PageRank |
0916-8508 | 2 | 0.41 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shinya Yamasaki | 1 | 2 | 0.41 |
| Shingo Nakaya | 2 | 2 | 0.41 |
| Shin'ichi Wakabayashi | 3 | 2 | 0.41 |
| Tetsushi Koide | 4 | 2 | 0.74 |