Paper Info
Title
Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits
Abstract
This paper presents a high speed inductor-less D flip-flop (DFF) architecture that works on the principle of equalization using two feedbacks. Feedback from the first latch output to the input results effectively in a linear equalizer, whereas the feedback of the flip-flop output to the input culminates in decision feedback equalization. The proposed feebackbased DFF designed in 90nm CMOS technology shows 37.5% improvement in speed, as compared to the conventional DFF without feedbacks. Post layout circuit simulations also show an overall 33.7% improvement in the speed of a high-speed PRBS generator when such feedbacks are added to conventional flipflops in it. Additionally, when this technique is used in a Hogge phase detector for clock and data recovery, 89% improvement in vertical eye opening and 73% reduction in pattern dependent jitter at the input of the phase detector is observed. In essence, the technique effectively achieves distributed equalization in highspeed communication circuits.
Year
DOI
Venue
2016
10.1109/TCSII.2016.2531098
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
CDR,Flips-flops,PRBS generator,clock and data recovery circuit,decision feedback equalizers,high-speed integrated circuits,inductorless
Clock signal,Equalization (audio),Control theory,Computer science,Pseudorandom binary sequence,Electronic engineering,CMOS,Bandwidth (signal processing),Jitter,Phase detector,Integrated circuit
Journal
Volume
Issue
ISSN
PP
99
1549-7747
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Mahendra Sakare141.94
Sarit K. Das2457.81
Shalabh Gupta37420.63