Name
Abstract | ||
|---|---|---|
In this paper, we propose an IP lookup scheme, called Helix, that performs parallel prefix matching at the different prefix lengths and uses the helicoidal properties of binary trees to reduce tree height. The reduction of the tree height is achieved without performing any prefix modification. Helix minimizes the amount of memory used to store long and numerous prefixes and achieves IP lookup and route updates in a single memory access. We evaluated the performance of Helix in terms of the number of memory accesses and amount of memory required for storing large IPv4 and IPv6 routing tables with up to 512,104 IPv4 and 389,956 IPv6 prefixes, respectively. In all the tested routing tables, Helix performs lookup in a single memory access while using very small memory amounts. We also show that Helix can be implemented on a single field-programmable gate array (FPGA) chip with on-chip memory for the IPv4 and IPv6 tables considered herein, without requiring external memory. Specifically, Helix uses up to 72% of the resources of an FPGA to accommodate the most demanding routing table, without performance penalties. The implementation shows that Helix may achieve lookup speeds beyond 1.2 billion packets per second (Gpps). |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1016/j.comnet.2015.07.012 | Computer Networks |
Keywords | Field | DocType |
IP lookup,Binary tree,One memory access,Helicoidal properties,Double helix,IPv6 lookup | Computer science,Parallel computing,Field-programmable gate array,Algorithm,Computing with Memory,Binary tree,Prefix,Chip,Gate array,Routing table,Auxiliary memory | Journal |
Volume | ISSN | Citations |
89 | 1389-1286 | 2 |
PageRank | References | Authors |
0.37 | 39 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Roberto Rojas-Cessa | 1 | 308 | 47.00 |
| Taweesak Kijkanjanarat | 2 | 6 | 1.82 |
| Wara Wangchai | 3 | 2 | 0.71 |
| Krutika Patil | 4 | 2 | 0.71 |
| Narathip Thirapittayatakul | 5 | 2 | 0.71 |