Name
Abstract | ||
|---|---|---|
Dividing last level caches into slices is a popular method to prevent memory accesses from becoming a bottleneck on modern multicore processors. In order to assess and understand the benefits of cache slicing in detail, a precise knowledge of implementation details such as the slice selection algorithm are of high importance. However, slice selection methods are mostly unstudied, and processor manufacturers choose not to publish their designs, nor their design rationale. In this paper, we present a tool that allows to recover the slice selection algorithm for Intel processors. The tool uses cache access information to derive equations that allow the reconstruction of the applied slice selection algorithm. Thereby, the tool enables further exploration of the behavior of modern caches. The tool is successfully applied to a range of Intel CPUs with different slices and architectures. Results show that slice selection algorithms have become more complex over time by involving an increasing number of bits of the physical address. We also demonstrate that among the most recent processors, the slice selection algorithm depends on the number of CPU cores rather than the processor model. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/DSD.2015.56 | Euromicro Symposium on Digital Systems Design |
Keywords | DocType | Volume |
Cache slices, Intel, last level cache, Prime and Probe | Journal | 2015 |
Citations | PageRank | References |
15 | 0.68 | 29 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gorka Irazoqui Apecechea | 1 | 258 | 12.16 |
| Thomas Eisenbarth | 2 | 840 | 61.33 |
| Berk Sunar | 3 | 956 | 68.31 |