Name
Title | ||
|---|---|---|
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. |
Abstract | ||
|---|---|---|
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1016/j.vlsi.2015.09.005 | Integration |
Keywords | Field | DocType |
Nonvolatile SRAM Cell,Emerging technology,Programmable Metallization Cell (PMC),Single Event Upset (SEU),Hybrid memory | nvSRAM,Soft error,Computer science,Error detection and correction,Static random-access memory,Electronic engineering,Transmission gate,Programmable metallization cell,Embedded system,Memory cell,Resistive random-access memory | Journal |
Volume | ISSN | Citations |
52 | 0167-9260 | 1 |
PageRank | References | Authors |
0.36 | 16 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pilin Junsangsri | 1 | 28 | 5.78 |
| Jie Han | 2 | 863 | 66.92 |
| Fabrizio Lombardi | 3 | 1985 | 259.25 |