Name
Abstract | ||
|---|---|---|
This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs).
The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and
adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in
terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure
which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other
2-D DWT structures require a fixed memory size. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/s00034-008-9068-1 | CSSP |
Keywords | Field | DocType |
DWT, Block-based scan method, Field programmable gate array, Lifting scheme | Internal memory,Lifting scheme,Adder,Computer science,Parallel computing,Field-programmable gate array,Second-generation wavelet transform,Discrete wavelet transform,Computer hardware,Wavelet transform,Auxiliary memory | Journal |
Volume | Issue | ISSN |
28 | 1 | 1531-5878 |
Citations | PageRank | References |
1 | 0.36 | 23 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sayed Ahmad Salehi | 1 | 31 | 3.78 |
| Saeed Sadri | 2 | 136 | 11.28 |