Title | ||
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Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses |
Abstract | ||
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Abstract Coupled switched capacitance causes crosstalk in ultra deep submicron/nanometer VLSI fabrication, which leads to power dissipation, delay faults, and logical malfunctions. We present the first memoryless transition bus-encoding technique for power minimization, error-correction, and elimination of crosstalk simultaneously. To accomplish this, we generalize balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. Optimal or asymptotically optimal constant weight codes eliminating each kind of crosstalk are constructed. |
Year | DOI | Venue |
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2015 | 10.1007/s10623-015-0084-4 | Designs, Codes and Cryptography |
Keywords | Field | DocType |
Constant weight codes,Packing sampling plan avoiding adjacent units,Crosstalk avoidance,Low power code,Packing by triples,Balanced sampling plan,94B25,05B40,05B07,62K10 | Discrete mathematics,Crosstalk,Dissipation,Error detection and correction,Theoretical computer science,Coding (social sciences),Electronic engineering,Sampling (statistics),Statistical design,Asymptotically optimal algorithm,Mathematics,Power minimization | Journal |
Volume | Issue | ISSN |
77 | 2 | 1573-7586 |
Citations | PageRank | References |
0 | 0.34 | 17 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Yeow Meng Chee | 1 | 593 | 62.01 |
Charles J. Colbourn | 2 | 2726 | 290.04 |
Alan Chi Hung Ling | 3 | 3 | 0.75 |
Hui Zhang | 4 | 11 | 3.75 |
Xiande Zhang | 5 | 52 | 15.19 |