Paper Info
Title
Enhanced pipelined architecture of H.264/AVC intra prediction.
Abstract
This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56MHz.
Year
DOI
Venue
2016
10.1016/j.image.2015.11.009
Signal Processing: Image Communication
Keywords
Field
DocType
H.264/AVC,Intra prediction,Pipeline,VLSI architecture
Data dependency,Entropy encoding,Context-adaptive variable-length coding,Computer science,Parallel computing,Theoretical computer science,Redundancy (engineering),Frame rate,Encoder,Macro,Encoding (memory)
Journal
Volume
Issue
ISSN
41
C
0923-5965
Citations 
PageRank 
References 
0
0.34
15
Authors
4
Name
Order
Citations
PageRank
Jiefeng Guo122.05
Zhixin Yang200.34
Jianwei Zheng311.37
Donghui Guo410721.93