Name
Abstract | ||
|---|---|---|
This brief presents a logarithmic analog-to-digital converter architecture with selectable transfer characteristic. A delay-matched regeneration detection circuit and the transfer characteristic selection method are also presented. The transfer characteristic selection can be used to improve both resolution and integral nonlinearity of the converter for larger input voltages. A transistor-level im... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCSII.2015.2503567 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Resistors,Delays,Transistors,Inverters,Analog-digital conversion,Logic gates | Integral nonlinearity,Logic gate,Microelectronics,Control theory,Voltage,Electronic engineering,Resistor,Logarithm,Design process,Transistor,Mathematics | Journal |
Volume | Issue | ISSN |
63 | 3 | 1549-7747 |
Citations | PageRank | References |
1 | 0.38 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mauro Santos | 1 | 1 | 0.38 |
| Nuno Cavaco Horta | 2 | 310 | 49.65 |
| Jorge Guilherme | 3 | 14 | 6.02 |