Title
Design of QPP Interleavers for the Parallel Turbo Decoding Architecture.
Abstract
Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increasing data rates motivated by throughput-intensive applications result in higher parallelism of turbo decoder design, rendering the efficient realization of the interleaver a highly challenging work. This paper addresses the design of quadratic permutation polynomial (QPP) interleaver for the symbol-ba...
Year
DOI
Venue
2016
10.1109/TCSI.2015.2512715
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Decoding,Iterative decoding,Writing,Hardware,Throughput,Clocks
Architecture,Sequential decoding,Computer science,Parallel computing,Serial concatenated convolutional codes,Turbo decoding,Electronic engineering,List decoding
Journal
Volume
Issue
ISSN
63
2
1549-8328
Citations 
PageRank 
References 
0
0.34
18
Authors
4
Name
Order
Citations
PageRank
Jian Wang100.68
Kangli Zhang261.94
Harald Kroll3175.08
Jibo Wei441944.40