Name
Abstract | ||
|---|---|---|
In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consumption of energy and time delay. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/s11390-015-1551-0 | Journal of Computer Science and Technology |
Keywords | Field | DocType |
network reliability, homogeneous fault, fault tolerance, reconfigurable system, network-on-chip | Graph,Colored,Computer science,Network simulation,Network on a chip,Computer network,Network topology,Real-time computing,Fault tolerance,Reliability (computer networking),Heterogeneous network,Distributed computing | Journal |
Volume | Issue | ISSN |
30 | 5 | 1860-4749 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rui Hou | 1 | 0 | 0.34 |
| Wu Jigang | 2 | 764 | 86.18 |
| Yawen Chen | 3 | 93 | 19.35 |
| Haibo Zhang | 4 | 169 | 27.72 |
| Xiufeng Sui | 5 | 27 | 5.83 |