Name
Abstract | ||
|---|---|---|
Trace-driven simulation has been widely used by designers and performance analyst to study and evaluate performance of computer systems. The increasing complexity benchmarks combined with the relatively slow rate of detailed performance analysis has resulted in a widening gap between the size of workloads and the speed of analysis. This has necessitated the use of reduced traces that represent the original workloads. Unfortunately, the existing methods of generating and validating reduced traces does not provide any guarantees regarding the representativeness of such traces. Trace-driven simulations based on unrepresentative reduced/sampled traces may, therefore, produce erroneous timer/simulator results. In this paper, we have presented a new methodology for generating and validating a reduced trace. Experimental results show effectiveness and usefulness of the proposed technique. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1145/271003.271006 | SIGARCH Computer Architecture News |
Field | DocType | Volume |
Trace driven simulation,Computer science,Parallel computing,Representativeness heuristic,Real-time computing,Sampling (statistics),Timer | Journal | 25 |
Issue | Citations | PageRank |
4 | 0 | 0.34 |
References | Authors | |
0 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Humayun Khalid | 1 | 16 | 6.17 |