Name
Title | ||
|---|---|---|
A Fast Settling All Digital Pll Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm |
Abstract | ||
|---|---|---|
This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27 x 0.36mm(2), is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25 degrees C is 3 mu s. The average reduction energy is at least 42% from 0 degrees C to 100 degrees C. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transfun.E98.A.2592 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
ADPLL, fast settling, digital calibration, timing error correction, temperature compensation | Settling,Phase-locked loop,Oscillation,Control theory,Mathematics | Journal |
Volume | Issue | ISSN |
E98A | 12 | 1745-1337 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keisuke Okuno | 1 | 5 | 3.80 |
| Shintaro Izumi | 2 | 82 | 31.56 |
| Kana Masaki | 3 | 0 | 0.34 |
| Hiroshi Kawaguchi | 4 | 395 | 91.51 |
| masahiko yoshimoto | 5 | 117 | 34.06 |