Name
Abstract | ||
|---|---|---|
We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The measured maximum integral nonlinearity (INL) of the proposed ADC is 1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transele.E98.C.489 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
ADC, I/O-size, VTC, MOM capacitance | Capacitor voltage,Electronic engineering,Input/output,Engineering | Journal |
Volume | Issue | ISSN |
E98C | 6 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keisuke Okuno | 1 | 5 | 3.80 |
| Toshihiro Konishi | 2 | 16 | 5.09 |
| Shintaro Izumi | 3 | 82 | 31.56 |
| masahiko yoshimoto | 4 | 117 | 34.06 |
| Hiroshi Kawaguchi | 5 | 395 | 91.51 |