Name
Abstract | ||
|---|---|---|
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transinf.2014RCP0004 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | DocType | Volume |
loop mapping, software pipelining, Dual-V-DD, low power, Graph Minor | Journal | E98D |
Issue | ISSN | Citations |
2 | 1745-1361 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bin Xu | 1 | 133 | 23.23 |
| shouyi yin | 2 | 579 | 99.95 |
| leibo liu | 3 | 816 | 116.95 |
| Shaojun Wei | 4 | 555 | 102.32 |