Name
Abstract | ||
|---|---|---|
A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transele.E98.C.45 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
protocol processor, communication SoC, software-hardware cooperation, PON, digital circuit, MAC | Digital electronics,Chip,Software,Engineering,Computer hardware,10G-EPON,Embedded system | Journal |
Volume | Issue | ISSN |
E98C | 1 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Miura Naoki | 1 | 87 | 9.80 |
| Akihiko Miyazaki | 2 | 3 | 0.88 |
| Junichi Kato | 3 | 0 | 0.34 |
| Nobuyuki Tanaka | 4 | 6 | 3.69 |
| Satoshi Shigematsu | 5 | 78 | 14.61 |
| Masami Urano | 6 | 9 | 2.91 |
| Mamoru Nakanishi | 7 | 76 | 13.25 |
| Tsugumichi Shibata | 8 | 10 | 3.62 |