Paper Info
Title
A Near-Threshold Cell-Based All-Digital Pll With Hierarchical Band-Selection G-Dco For Fast Lock-In And Low-Power Applications
Abstract
This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5M(F) (M-F = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm(2). In near-threshold region (V-DD = 0.36 V), the proposed ADPLL only dissipates 68.2 mu W and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V V-DD operation, the proposed ADPLL dissipates 404.2 mu W at 400 MHz. The fast lock-in time of 4.489 mu s and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.
Year
DOI
Venue
2015
10.1587/transele.E98.C.882
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
all-digital phase-locked loop, hierarchical digitally controlled oscillators, low voltage, low power, fast lock-in, low jitter
Phase-locked loop,Band selection,Electronic engineering,Low voltage,Engineering,Low jitter
Journal
Volume
Issue
ISSN
E98C
8
1745-1353
Citations 
PageRank 
References 
0
0.34
10
Authors
3
Name
Order
Citations
PageRank
Chia-Wen Chang118116.85
Yuan-Hua Chu2202.20
Shyh-Jye Jou3420275.67