Title
Low-Power Motion Estimation Processor With 3d Stacked Memory
Abstract
Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60 fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.
Year
DOI
Venue
2015
10.1587/transfun.E98.A.1431
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Keywords
Field
DocType
3DIC design, motion estimation processor, low power design, memory stacking
Semiconductor memory,Parallel computing,Motion estimation,Mathematics
Journal
Volume
Issue
ISSN
E98A
7
0916-8508
Citations 
PageRank 
References 
1
0.36
9
Authors
5
Name
Order
Citations
PageRank
Shuping Zhang141.83
Jinjia Zhou213829.30
Dajiang Zhou335550.25
Shinji Kimura46017.59
Satoshi Goto51006142.14