Name
Title | ||
|---|---|---|
Low-Jitter Design For Second-Order Time-To-Digital Converter Using Frequency Shift Oscillators |
Abstract | ||
|---|---|---|
We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64 dB is achievable at an input signal frequency of 10 kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transfun.E98.A.1475 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
TDC, FSO, jitter, design methodology | Frequency shift,Oscillation,Control theory,Electronic engineering,Theoretical computer science,Design methods,Jitter,Low jitter,Time-to-digital converter,Mathematics | Journal |
Volume | Issue | ISSN |
E98A | 7 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keisuke Okuno | 1 | 5 | 3.80 |
| Toshihiro Konishi | 2 | 16 | 5.09 |
| Shintaro Izumi | 3 | 82 | 31.56 |
| masahiko yoshimoto | 4 | 117 | 34.06 |
| Hiroshi Kawaguchi | 5 | 395 | 91.51 |