Paper Info
Title
A Varactor-Based All-Digital Multi-Phase Pll With Random-Sampling Spur Suppression Techniques
Abstract
This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.
Year
DOI
Venue
2016
10.1587/transele.E99.C.481
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
all-digital phase-locked loop, digitally controlled oscillator, low voltage, spur suppression, low jitter, low spur
Digitally controlled oscillator,Phase-locked loop,Linearity,Spur,Electronic engineering,dBc,Engineering,Jitter,Electrical engineering,Clock rate,Varicap
Journal
Volume
Issue
ISSN
E99C
4
1745-1353
Citations 
PageRank 
References 
0
0.34
11
Authors
6
Name
Order
Citations
PageRank
Chia-Wen Chang118116.85
Kai-Yu Lo200.68
Hossameldin A. Ibrahim300.34
Ming-Chiuan Su431.80
Yuan-Hua Chu5202.20
Shyh-Jye Jou6420275.67