Name
Abstract | ||
|---|---|---|
In this paper, we design a hardware and energy-efficient stochastic lower-upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with r... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2446481 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Stochastic processes,MIMO,Matrix decomposition,Hardware,Accuracy,Signal to noise ratio,Very large scale integration | Logic gate,Computer science,Matrix decomposition,MIMO,Stochastic process,Multiplier (economics),Electronic engineering,Computer hardware,Very-large-scale integration,LU decomposition,Computation | Journal |
Volume | Issue | ISSN |
24 | 4 | 1063-8210 |
Citations | PageRank | References |
4 | 0.45 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jienan Chen | 1 | 84 | 13.64 |
| Hu Jianhao | 2 | 96 | 20.56 |
| Jiangyun Zhou | 3 | 5 | 1.83 |