Paper Info
Title
A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators.
Abstract
Barriers that prevent programmers from using FPGAs include the need to work within vendor specific CAD tools, knowledge of hardware programming models, and the requirement to pass each design through synthesis, place and route. In this work, a dynamic overlay is designed to support Just- In-Time assembly by composing hardware operators to construct full accelerators. The hardware operators are pre-synthesized bit- streams and can be downloaded to Partially Reconfigurable(PR) regions at runtime.
Year
Venue
Field
2016
arXiv: Hardware Architecture
Computer science,Real-time computing,Operator (computer programming),Overlay,Computer hardware,Cad tools,Computer architecture,Programming paradigm,Parallel computing,Place and route,Field-programmable gate array,Vendor,Embedded system
DocType
Volume
Citations 
Journal
abs/1603.01187
0
PageRank 
References 
Authors
0.34
4
3
Name
Order
Citations
PageRank
Zeyad Aklah1202.59
Sen Ma2235.31
David Andrews3216.90