Title
A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes.
Abstract
This letter presents a heuristic technique for simplifying the parity-check node operation in a relaxed min-sum iterative decoder. The proposed decoder eliminates the second-minimum computation in check nodes, which allows broadcasting the same output to all neighboring variable nodes to alleviate routing problem in VLSI implementations of low-density parity check (LDPC) decoders. The second-minimum, when required, is emulated by adding an offset to the first-minimum. The proposed relaxed decoder also uses a relaxation factor equal to 0.5 to simplify variable nodes. Simulation results for two LDPC codes show the proposed decoding algorithm with only 4-bit quantization closely matches the performance of floating-point normalized/offset min-sum and sum-product decoders in the waterfall region.
Year
DOI
Venue
2016
10.1109/LCOMM.2016.2517142
IEEE Communications Letters
Keywords
Field
DocType
Decoding,Iterative decoding,Encoding,Complexity theory,Wires,Partitioning algorithms
Broadcasting,Parity bit,Heuristic,Computer science,Low-density parity-check code,Algorithm,Theoretical computer science,Real-time computing,Decoding methods,Quantization (signal processing),Offset (computer science),Encoding (memory)
Journal
Volume
Issue
ISSN
20
3
1089-7798
Citations 
PageRank 
References 
2
0.38
12
Authors
3
Name
Order
Citations
PageRank
Saied Hemati111913.64
François Leduc-Primeau2156.73
Warren J. Gross31106113.38