Title
An embedded system for handwritten digit recognition
Abstract
The goal of this work is the design and implementation of a low-cost system-on-FPGA for handwritten digit recognition, based on a relatively deep and wide network of perceptrons. In order to increase the performance of the application on embedded processors whose performances are way below standard general purpose CPUs, a regularization method was used during the training phase of the neural network that allows for the drastic reduction of floating point operations. Our implementation achieves a 3 × speed-up toward a raw implementation without optimization, while keeping the accuracy in acceptable ranges. Our efforts reinforce the fact that FPGAs are suited for deploying complex artificial intelligence modules.
Year
DOI
Venue
2015
10.1016/j.sysarc.2015.07.015
Journal of Systems Architecture - Embedded Systems Design
Keywords
Field
DocType
Neural network,Soft processor,Regularization,Image processing
General purpose,Computer science,Floating point,Parallel computing,Field-programmable gate array,Image processing,Regularization (mathematics),Digit recognition,Artificial neural network,Perceptron,Embedded system
Journal
Volume
Issue
ISSN
61
10
1383-7621
Citations 
PageRank 
References 
0
0.34
6
Authors
2
Name
Order
Citations
PageRank
Luca Bochi Saldanha171.79
Christophe Bobda262790.57