Name
Title | ||
|---|---|---|
Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol. 12 (2015) No. 5 pp. 20150102] |
Year | Venue | DocType |
|---|---|---|
2015 | IEICE Electronic Express | Journal |
Volume | Issue | Citations |
12 | 7 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chunyu Peng | 1 | 30 | 10.29 |
| Youwu Tao | 2 | 3 | 0.77 |
| Wenjuan Lu | 3 | 10 | 2.96 |
| Zhengping Li | 4 | 3 | 1.11 |
| Xinchun Ji | 5 | 3 | 0.77 |
| Jinlong Yan | 6 | 4 | 1.93 |
| Junning Chen | 7 | 3 | 1.11 |