Paper Info
Title
Optimal processor dynamic-energy reduction for parallel workloads on heterogeneous multi-core architectures
Abstract
With the increase in the number of cores in processor chips observed in recent years, design choices-such as the number of cores in chip, the amount of resources per core, and whether to design homogeneous or heterogeneous chips-need to be given proper support. Several studies on heterogeneous multi-core processors are concerned with performance improvements. In this work, we propose mathematical models to analyze some of these design issues with focus on the reduction of processor dynamic energy. In particular, these models allow the comparison of the dynamic-energy consumption of multi-core architectures when they execute a workload in the same amount of time while allowing different core operating frequency between the compared architectures. The results of the analysis allow chip designers to choose the right conditions for optimal energy savings in heterogeneous multi-core chips based on the parallel fraction of the workloads and on the distributions of the resources among the cores in the chip. Under a simplified context, the devised models agree with the consolidated knowledge that heterogeneous multi-core chips have considerable advantage over homogeneous multi-core and single-core architectures in terms of energy efficiency.
Year
DOI
Venue
2015
10.1016/j.micpro.2015.05.009
Microprocessors and Microsystems: Embedded Hardware Design
Keywords
Field
DocType
CMOS power,Energy savings,Heterogeneous architectures,Multi-core processors,Parallel scalability
Operating frequency,Workload,Homogeneous,Efficient energy use,Computer science,Parallel computing,Real-time computing,Chip,Dynamic energy,Mathematical model,Multi-core processor
Journal
Volume
Issue
ISSN
39
6
0141-9331
Citations 
PageRank 
References 
2
0.41
19
Authors
4
Name
Order
Citations
PageRank
Carlos A. Barros140.79
Luiz Felipe Q. Silveira2196.32
Carlos Valderrama311218.13
Samuel Xavier-de-Souza47910.07