Name
Abstract | ||
|---|---|---|
With the availability of high-performance, low-power microprocessors, portable computing is becoming commonplace. The prevalence of portable computers makes them the most obvious examples of systems in which power requirements are a significant design issue. This paper addresses the power tradeoffs of an important component of modern memory hierarchies: second-level caches. Thought by some to increase the total system power requirements, second-level caches can actually reduce the power consumed by the memory hierarchy — in addition to improving the overall performance. Power is saved by substituting second-level cache accesses for main memory accesses; given current memory technology, an active second-level cache and an idle main memory require less total power than an active memory by itself. Clearly, the amount of power saved depends on the extent to which main memory accesses are reduced. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1016/S0141-9331(97)00051-3 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Cache,Memory hierarchy,Power consumption,Low power,Trace-driven simulation | Registered memory,Interleaved memory,Semiconductor memory,Uniform memory access,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Memory management,Memory map,Computer memory | Journal |
Volume | Issue | ISSN |
21 | 5 | 0141-9331 |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Kelly Flanagan | 1 | 57 | 9.92 |
| James K. Archibald | 2 | 632 | 161.01 |
| Jun Su | 3 | 1 | 0.37 |