Name
Abstract | ||
|---|---|---|
This paper presents the results of a simulation study related to cache design for CMOS microprocessors. It compares direct mapping and set associative mapping, for small on-chip caches, in the design environment dictated by advanced CMOS technology (the ratio of off-chip to on-chip delays is relatively high). Parameters of the study include cache size, block size and number of blocks per set (for set associative mapping). The major purpose of the work was to determine numerically the impact of various mapping parameters on the performance of relatively small on-chip caches in general, and for one RISC-style microprocessor in particular which is similar to the MIPS architecture. The study was conducted using a representative set of benchmark programs (used previously for the analysis of RISC-type microprocessors). Results are presented for two benchmarks that represent workload extremes. |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1016/0141-9331(88)90163-9 | Microprocessors and Microsystems |
Keywords | Field | DocType |
microprocessors,RISCs,cache memory,simulation | Block size,Associative property,Computer science,Cache,CPU cache,Parallel computing,Microprocessor,CMOS,Real-time computing,Cache algorithms,Cache coloring | Journal |
Volume | Issue | ISSN |
12 | 4 | 0141-9331 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Chow | 1 | 0 | 0.34 |
| T. Geigel | 2 | 0 | 0.34 |
| V. Milutinović | 3 | 2 | 1.08 |
| J. Pridmore | 4 | 0 | 0.34 |