Name
Title | ||
|---|---|---|
Anytime system level verification via parallel random exhaustive hardware in the loop simulation |
Abstract | ||
|---|---|---|
System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1016/j.micpro.2015.10.010 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Model Checking of Hybrid Systems,Model checking driven simulation,Hardware in the loop simulation | Functional verification,Model checking,Simulation,Computer science,Intelligent verification,Parallel computing,Runtime verification,Real-time computing,Hardware-in-the-loop simulation,High-level verification,Hybrid system,Formal verification | Journal |
Volume | Issue | ISSN |
41 | C | 0141-9331 |
Citations | PageRank | References |
4 | 0.38 | 30 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toni Mancini | 1 | 240 | 25.98 |
| Federico Mari | 2 | 140 | 12.26 |
| Annalisa Massini | 3 | 137 | 15.53 |
| Igor Melatti | 4 | 217 | 19.48 |
| Enrico Tronci | 5 | 336 | 35.83 |