Name
Abstract | ||
|---|---|---|
In recent years rising complexity, shrinking silicon feature sizes, and reduced design cycles have posed new challenges on the verification of modern system-on-chip solutions. To tackle the issues caused by the rising complexity various design and verification languages, as well as methodologies and tools have been introduced. Likewise, new and better physical process models allow for improved simulation of both analog and digital designs. Finally, strict management plans are used to cope with the shrinking design and verification cycles. Despite all these efforts, however, many problems exist in industrial state-of-the-art processes and tools. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/s00502-015-0314-5 | Elektrotechnik und Informationstechnik |
Keywords | Field | DocType |
system-on-chip, pre- and post-silicon verification, user-mode testing, System-on-Chip, Verifikation, User-Mode-Test | Functional verification,System on a chip,Systems engineering,Intelligent verification,Process modeling,Runtime verification,Engineering | Journal |
Volume | Issue | ISSN |
132 | 6 | 1613-7620 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Horauer | 1 | 64 | 13.46 |
| Widhalm, D. | 2 | 0 | 1.69 |
| Stefan Tauner | 3 | 0 | 0.68 |
| Stefan Mirtl | 4 | 0 | 0.34 |