Name
Title | ||
|---|---|---|
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment |
Abstract | ||
|---|---|---|
Nowadays, systems involving multiple FPGAs are used for various scientific applications. Such systems require a data bus dedicated to the communication between FPGAs, which could be done through a LVDS type. Another important factor is that the routing that interconnects the LVDS pins on the platform should be precisely developed to avoid instabilities in communication. Unfortunately, many platforms available in the market do not observe such restrictions, limiting the throughput of the bus. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1186/s13173-015-0026-z | J. Braz. Comp. Soc. |
Keywords | Field | DocType |
LVDS, FPGA, CRC, Communication inter-FPGAs | Data structure,Computer science,Field-programmable gate array,Communication channel,Error detection and correction,Throughput,System bus,Limiting,Embedded system | Journal |
Volume | Issue | ISSN |
21 | 1 | 1678-4804 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lucas T. Melo | 1 | 0 | 0.34 |
| S. H. C. Santana | 2 | 0 | 0.34 |
| Abel Guilhermino Silva-Filho | 3 | 62 | 12.94 |
| Manoel Eusebio de Lima | 4 | 29 | 8.12 |
| Victor Wanderley Costa de Medeiros | 5 | 0 | 1.01 |
| M. L. M. Marinho | 6 | 0 | 0.34 |