Name
Abstract | ||
|---|---|---|
Phase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics including low static power consumption and high density. However, long write latency is one of the major drawbacks in current PCM technology. Since the write latency of SET and RESET operation of PCM is asymmetric, the much slower SET operation determines the write latency. Recent study has shown that applying the write-once-memory-code (WOM-code) to PCM enables RESET-only writes when the memory rows are written back into PCM, which helps to reduce the write latency effectively. Whereas applying WOM-code to PCM significantly reduces the write latency, it comes at the overhead of huge memory capacity in resource-constrained embedded systems. In this paper, based on the memory organization that a small WOM-Buffer attached with the original PCM, we propose a novel memory block management scheme implemented at memory controller to apply WOM-code only to write-intensive memory blocks, which can efficiently reduce write latency with less PCM capacity overhead. Experiments show that our memory block management scheme reduces write latency of PCM by 38.5% and reduces read latency by 30.8% with only a 4.68% PCM capacity overhead. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/HPCC-CSS-ICESS.2015.178 | HPCC/CSS/ICESS |
Keywords | Field | DocType |
phase change memory,write latency,main memory,embedded system,WOM-code | Registered memory,Phase-change memory,Semiconductor memory,Interleaved memory,Computer science,Real-time computing,Memory management,Memory map,Computer hardware,Memory controller,Memory refresh | Conference |
ISSN | Citations | PageRank |
2576-3504 | 0 | 0.34 |
References | Authors | |
19 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kun Ling | 1 | 0 | 0.34 |
| Lei Ju | 2 | 265 | 29.03 |
| Cai Xiaojun | 3 | 19 | 4.14 |
| zhiping jia | 4 | 463 | 60.64 |